1. Field of the Invention:
This invention relates generally to an insulated-gate field-effect transistor, and more particularly, to an insulated-gate field-effect transistor in which a source region is formed by diffusion of two kinds of impurities and a drain region is also formed by diffusion of two kinds of impurities, the two kinds of impurities having different diffusion depths.
2. Description of the Prior Art
In the conventional n-type channel insulated-gate field-effect transistor, for example, the n-type channel metal oxide semiconductor field-effect transistor (MOSFET), thermal diffusion of phosphorus is used in order to form n-type source and drain regions in a p-type silicon substrate.
However, if it is desired that the channel length should be shortened to 5 .mu.m, for example, in order to produce a MOSFET having a highspeed of operation, control of the channel length is very difficult, because diffusion of phosphorus in the horizontal direction may not be ignored. As a result thereof, punch-through between source and drain regions is apt to occur, and consequently it is difficult to produce a MOSFET having high-reproducibility and a uniform characteristics.
On the other hand, arsenic, which can be diffused into a silicon substrate to form an n-type conductive layer in the same manner as phosphorus, has a low diffusion coefficient in comparison to that of phosphorus, and creates less crystal distortion because its atomic radius is similar to that of silicon. Furthermore, the concentration gradient of arsenic in the diffused layer of arsenic is steep, and therefore diffusion of arsenic in the horizontal direction is small; and the diffusion concentration profile is not easily changed in the heat treatment steps after diffusion because arsenic does not diffuse readily at the normal heat treatment temperature. Accordingly, it can be said that arsenic is a superior impurity which can improve the accuracy of diffusion control.
However, it is difficult to diffuse arsenic at high concentrations into a silicon substrate under the most suitable conditions for forming the MOSFET, and also difficult to diffuse arsenic into the substrate with the desirable depth. In accordance with our studies, for an arsenic-glass layer of 2,000 A thick (arsenic concentration : 6 .times. 10.sup.21 /cm.sup.3) deposited on a silicon substrate and diffused into the silicon substrate at the temperature of 1,000.degree. C for 30 minutes, the surface resistance .rho..sub.s of the n-type layer obtained by the above-mentioned treatment was 50 .OMEGA./.sub..quadrature., and the depth of diffusion was 0.2 .mu.m.
Consequently, it is difficult to lower the surface resistance sufficiently even though the source region and the drain region are formed by the diffusion of arsenic. Therefore, even though the channel length is sufficiently reduced, it is difficult to secure the speed-up of operation of the MOSFET. Moreover, since the depth of the diffused region of arsenic is shallow, diffused aluminum used as electrodes can push through the source or drain region, and as a result abnormal leakage current can flow.